FIG. 1 shows a schematic block diagram of an LDO (low-dropout) linear voltage regulator (100) with high power supply rejection (PSR). The LDO linear voltage regulator is commonly referred to as simply “LDO.” As shown in FIG. 1, The feedback network (101), including a resistor divider and an error amplifier (102), regulates the DC output voltage Vout to a desired level. The error amplifier (102) may be a single stage or multi-stage amplifier. The pass transistor Mpass may be either a field effect transistor (FET) or a bipolar transistor, and may be of either n-type or p-type. Multi-stage and high-gain amplifiers are typically used as the implementation of the error amplifier in the feedback network circuitry. Improved implementations of the feedback network (101), in accordance with embodiments of the invention, are shown in FIGS. 2 and 3.
Further as shown in FIG. 1, the supply rejection network (103) replicates the input ripples at the gate of the pass transistor Mpass to achieve high PSR. The supply rejection network (103) is shown in FIG. 1 in a feed-forward network configuration and may be adapted to change the amplitude of the replicated ripples at the gate of the transistor Mpass for different values of output load.